Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 437

14.6.2 PLL and Reset Control Register (PLPRCR)
The 32-bit system PLL and reset control register (PLPRCR), shown in
system frequency and low-power mode operation.
0
Field
HRESET
POR
R/W
Addr
16 17
Field — TEXPS
HRESET — 1
POR 0 1
R/W
Addr
Notes: HRESET is hard reset and POR is power-on reset. * POR depends on the combination of MODCK1 and
MODCK2. See Table 14-5
This register is affected by HRESET and SRESET.
Bits Name
0–4 MFN Numerator of the fractional part of the multiplication factor in the formula for the output frequency of
the DPLL and Interface. The range of values for the MFN is 0 to 31. The numerator of the fractional
part of the multiplication factor (MFN) must be less than the denominator of the fractional part of the
multiplication factor (MFD+1).
frequency will differ from the desired frequency. If the numerator is zero, the circuit for fractional
division is disabled to save power.
Refer to
5–9 MFD Denominator minus 1 of the fractional part of the multiplication factor in the formula for the output
frequency of the DPLL and Interface.The range of values for the MFD is 1 to 31. The denominator
of the fractional part of the multiplication factor(MFD+1) must be greater than the numerator of the
fractional part of the multiplication factor MFN.
output clock frequency will differ from the desired frequency. If the numerator is zero, the circuit for
fractional division is disabled to save power.
Refer to
10–11 S Selection Bits for the Divider after the Double Clock (fdck)
00 Divide By 1
01 Divide By 2
10 Divide By 4
11 = Reserved.
Refer to
Freescale Semiconductor
4 5
MFN
—
0000
(IMMR & 0xFFFF0000) + 284
18 19 20 21
— – — CSRC
0 0 0 0
0 0 0 0
(IMMR & 0xFFFF0000) + 286
for more information.
Figure 14-13. PLL and Reset Control Register (PLPRCR)
Table 14-9. PLPRCR Field Descriptions
1
If the numerator is larger than the denominator, the output clock
Section 14.2.2, "Digital Phase Lock Loop and Interface."
Section 14.2.2, "Digital Phase Lock Loop and Interface."
Section 14.2.2, "Digital Phase Lock Loop and Interface."
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Figure
9 10
MFD
— —
00001 0
R/W
22 23 24 25 26
– CSR — FIOPD
0 — — —
0 0 0 0
R/W
Table 14-9 describes PLPRCR bits.
Description
1
If the numerator is larger than the denominator, the
Clocks and Power Control
14-13, is used to control the
11 12 15
S MFI
— —
*
1
27 30 31
PDF DBRMO
0000 0
*
0
14-21