Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 581

18.8.1 RISC Timer Table Scan Algorithm
The CP scans the timer table once every tick of the internal CP timer. For each valid timer in the table, the
CP decrements the count and checks for a timeout. If no timeout occurs, it moves to the next timer. If a
timeout does occur, the CP sets the corresponding event bit in RTER and checks R_TMR to see if the timer
must be restarted. If it does, the CP leaves the timer valid bit set in the R_TMV register and resets the
current count to the initial count; otherwise, the CP clears R_TMV. When the timer table is scanned, the
CP updates TM_CNT and stops working on the timer table until the next scan tick.
If is issued, the CP makes the appropriate modifications to the timer table and parameter RAM,
SET TIMER
but does not scan the timer table until the next tick of the internal CP timer. (Using
synchronizes the timer table modifications to the execution of the CP.)
18.8.2 The
SET TIMER
Issued to the CP command register (CPCR), the
configure the 16 timers in the RISC timer table. Set up the TM_CMD value in the RISC timer table
parameter RAM before writing 0x0851 to the CPCR.
18.8.3 RISC Timer Table Parameter RAM and Timer Table Entries
Two areas of dual-port RAM are used for the RISC timer table—RISC timer table parameter RAM and
the RISC timer table entries; see
DPRAM_BASE + 0x1DB0
Freescale Semiconductor
Command
SET TIMER
Figure 18-8.
16 RISC
Timer Table
Entries
(Up to 64 Bytes)
TM_BASE
RISC
Timer Table
Parameter RAM
Figure 18-8. RISC Timer Table RAM Usage
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Communications Processor
SET TIMER
command is used to enable, disable, and
Timer Table Base Pointer
properly
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