Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 461

Figure 15-17 shows CS as defined by the setup time required between the address lines and CE. The user
can configure ORx[ACS] to specify CS to meet this requirement.
Address
Figure 15-17. GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0)
15.5.1.2 Chip-Select and Write Enable Deassertion Timing
Figure 15-18 shows a basic connection between the MPC885 and a static memory device. Here, CS is
connected directly to CE of the memory device. The WE signals are connected to the respective W signal
in the memory device where each WE corresponds to a different data byte.
Freescale Semiconductor
MPC885
Address
CS
R/W
Data
Figure 15-16. GPCM Peripheral Device Interface
Clock
TS
TA
ACS = 11
ACS = 10
CS
R/W
Data
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Memory Controller
Peripheral
Address
CE
R/W
Data
15-21