Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 634

Powerquicc family

Table of Contents

Serial Interface

data stream over the first B channel. This SCC is configured for HDLC mode if V.120 rate adaptation is

required. The second B channel is then routed to the CODEC as a digital voice channel, if preferred. The

SPI is used to send initialization commands and periodically check status from the S/T transceiver. The

SMC connected to the terminal is configured for UART.

The MPC885 can identify and support each IDL channel or it can output strobe lines for interfacing with

devices that do not support the IDL bus. The IDL signals for each transmit and receive channel are as

L1RCLKx—IDL clock. Input to the MPC885

L1RSYNCx—IDL sync signal. Input to the MPC885. This signal indicates that the clock periods

following the pulse designate the IDL frame

L1RXDx—IDL receive data. Input to the MPC885. Valid only for bits supported by the IDL;

ignored for other signals that may be present

L1TXDx—IDL transmit data. Output from the MPC885. Valid only for bits supported by the IDL;

otherwise, three-stated

L1RQx—IDL request permission to transmit on the D channel. Output from the MPC885 on

L1GRx—IDL grant permission to transmit on the D channel. Input to the MPC885 on L1TSYNCx

The basic rate IDL bus has three channels:

B1 is a 64-Kbps bearer channel

B2 is a 64-Kbps bearer channel

D is a 16-Kbps signaling channel

System Bus (ROM and RAM)

Figure 20-25. ISDN Terminal Adaptor Using IDL

MPC885 PowerQUICC Family Reference Manual, Rev. 2

CODEC/Filter

Mono circuit

Freescale Semiconductor