Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 636

Serial Interface
20.2.5.2 Programming the IDL Interface
To program the IDL interface, first program SIMODE[GMx] to the IDL grant mode for that channel. If the
receive and transmit sections interface to the same IDL bus, set SIMODE[CRTx] to internally connect the
Rx clock and sync signals to the transmit section. Then program the SI RAM used for the IDL channels to
the preferred routing. See
Define the IDL frame structure by programming SIMODE[xFSD] to have a 1-bit delay from frame sync
to data, SIMODE[FE] to sample the sync on the falling edge, and SIMODE[CE] to transmit on the rising
edge of the clock. Program L1TXDx to be three-stated when inactive via the parallel I/O open-drain
register. To support the D channel, set the appropriate SICR[GR] bit and program the RAM entry to route
data to the chosen SCC. The two definitions of IDL, 8- and 10-bit, are only supported by modifying the SI
RAM programming. In both cases, L1GRx is sampled with L1TSYNCx and transferred to the D-channel
SCC as a grant indication. Repeat the same procedure for an IDL bus on the second TDM channel.
For example, based on the same 10-bit format as in
implement an IDL bus using SCC2, SCC3, and SMC2 connected to the TDM channel as follows:
1. Program both the Rx and Tx sections of the SI RAM as in
0x0001_0000.
Entry
Number
SWTR
1 0
2 0
3 0
4 0
5 0
2. SIMODE = 0x8000_0145. Only TDMa is used. SMC2 is connected to the TSA.
3. SICR = 0x00C0_4000. SCC2 and SCC3 are connected to the TSA. SCC3 supports the grant
mechanism since it is on the D channel.
4. PAODR[9] = 1. Configure L1TXDa to be an open-drain output.
5. PAPAR[7–9] = 0b111. Configure L1TXDa, L1RXDa, and L1RCLKa.
6. PADIR[7–9] = 0b011. Configure L1TXDa, L1RXDa, and L1RCLKa.
7. PCPAR[5,4] = 1. Configure L1TSYNCa, and L1RSYNCa.
8. L1TSYNCa performs the L1GRa grant function and is therefore an input but does not need to be
configured by clearing PCDIR. L1RSYNCa is an input but does not need to be configured in
PCDIR.
9. PDPAR[6] Configure L1RQa,
10. PCDIR[6] = 0. L1RQa is an output. SIGMR = 0x04. Enable TDMa (one static TDM).
11. SICMR is not used.
20-30
Section 20.2.3.8, "SI RAM Programming Example."
Table 20-11. SI RAM Settings for IDL Interface
SSEL CSEL CNT
0000 010 0000
0000 011 0000
0000 000 0000
0000 110 0000
0001 011 0000
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Section 20.2.3.8, "SI RAM Programming Example,"
Table 20-11. Write unused entries with
SI RAM
BYT LST
1 0 8 bits SCC2 (B1)
0 0 1 bit SCC3 (D)
0 0 1 bit no support
1 0 8 bits SMC2 (B2)
0 1 1 bit SCC3 (D) and strobe1
Description
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