Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 420

Clocks and Power Control
It is possible to use both clock sources in a system, with each providing
reference for different functions. If either reference source is not used, its
input should be grounded. It is not recommended to select the crystal
oscillator circuit as OSCLK while also driving a high-frequency clock
source on EXTCLK. This is because noise from the EXTCLK clock source
will couple into the crystal oscillator circuit and will in many cases not allow
the digital phase-locked loop (DPLL) to lock. The converse, however, is
allowable; EXTCLK can be selected as OSCLK while the crystal oscillator
circuit supplies a separate frequency reference.
A typical configuration uses a canned oscillator with the EXTCLK input selected as OSCLK, and uses a
10MHz crystal at EXTAL and XTAL to provide PITCLK.
There are 4 different PLL Modes defined by the MODCK pins at reset that determine the initial value of
the PLPRCR register. Three of these modes require a 10 MHz input frequency, while the fourth mode can
accept from 45 to 66 MHz. After reset, the PLPRCR can be programmed to achieve a different general
system clock as long as the following requirements are met.
• OSCM is 10 MHz only (MODCK = 00 or 01)
• EXTCLK is 10 MHz (MODCK = 11)
• EXTCLK is 45 MHz to 66 MHz (MODCK = 10)
The Input Frequency Requirements at reset are shown in
MODCK[1:2]
00, 01 OSCM = 10 MHz
11 EXTCLK = 10 MHz
45 MHz ≤ EXTCLK ≤ 66 MHz
10
14.2.2 Digital Phase Lock Loop and Interface
The programmable digital phase lock loop (DPLL) in the MPC885 generates the overall system operating
frequency in integer and non-multiples of the input clock frequency. CLKOUT synchronization is not
guaranteed for non-integer multiples of OSCLK. If CLKOUT is an integer multiple of OSCLK/EXTCLK,
the rising edge of EXTCLK is aligned (locked/synchronized) with the rising edge of CLKOUT. For a non
integer multiple of EXTCLK, this synchronization is lost, and the rising edges of EXTCLK and CLKOUT
have a continuously varying phase skew.
14-4
NOTE
Table 14-1. The Input Frequency Requirements
Freq. In
10 MHz ≤ EXTCLK /
(PDF+1) ≤ 32 MHz
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Table 14-1
PDF MFI, MFN, MFD for DPGDCK
0 160 MHz < OSCLK * 2 * (MFI + (MFN /
(MFD+1))) < 320 MHz
0 160 MHz < OSCLK * 2 * (MFI + (MFN /
(MFD+1))) < 320 MHz
160 MHz < OSCLK * 2 * (MFI + (MFN /
(MFD+1))) / (PDF+1) < 320 MHz
Freescale Semiconductor