Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 58

Figure
Number
26-9 SCC Status Registers (SCCS) ............................................................................................. 26-15
27-1 Ethernet Frame Structure ...................................................................................................... 27-1
27-2 Ethernet Block Diagram........................................................................................................ 27-2
27-3 Connecting the MPC885 to Ethernet .................................................................................... 27-5
27-4 Ethernet Address Recognition Flowchart ........................................................................... 27-12
27-5 Ethernet Mode Register (PSMR) ........................................................................................ 27-15
27-6 SCC Ethernet RxBD ........................................................................................................... 27-16
27-7 Ethernet Receiving Using RxBDs....................................................................................... 27-18
27-8 SCC Ethernet TxBD............................................................................................................ 27-19
27-9 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM) ......................................... 27-20
27-10 Ethernet Interrupt Events Example ..................................................................................... 27-21
28-1 Sending Transparent Frames between MPC885 ................................................................... 28-4
28-2 SCC Transparent Receive Buffer Descriptor (RxBD) .......................................................... 28-8
28-3 SCC Transparent Transmit Buffer Descriptor (TxBD) ......................................................... 28-9
28-4 SCC Transparent Event Register (SCCE)/Mask Register (SCCM).................................... 28-11
28-5 SCC Status Register in Transparent Mode (SCCS) ............................................................ 28-12
29-1 SMC Block Diagram............................................................................................................. 29-1
29-2 SMC Mode Registers (SMCMRn)........................................................................................ 29-3
29-3 SMC Memory Structure........................................................................................................ 29-5
29-4 SMC Function Code Registers (RFCR/TFCR)..................................................................... 29-7
29-5 SMC UART Frame Format................................................................................................. 29-10
29-6 SMC UART Receive BD (RxBD) ...................................................................................... 29-14
29-7 SMC UART Receiving using RxBDs ................................................................................. 29-16
29-8 SMC UART Transmit BD (TxBD) ..................................................................................... 29-17
29-9 SMC UART Event Register (SMCE)/Mask Register (SMCM) ......................................... 29-18
29-10 SMC UART Interrupts Example......................................................................................... 29-19
29-11 Synchronization with SMSYNx.......................................................................................... 29-23
29-12 Synchronization with the TSA............................................................................................ 29-24
29-13 SMC Transparent Receive BD (RxBD) .............................................................................. 29-26
29-14 SMC Transparent Transmit BD (TxBD)............................................................................. 29-27
29-15 SMC Transparent Event Register (SMCE)/Mask Register (SMCM) ................................. 29-29
29-16 SMC GCI Monitor Channel RxBD..................................................................................... 29-33
29-17 SMC GCI Monitor Channel TxBD..................................................................................... 29-34
29-18 SMC C/I Channel RxBD..................................................................................................... 29-34
29-19 SMC C/I Channel TxBD..................................................................................................... 29-35
29-20 SMC GCI Event Register (SMCE)/Mask Register (SMCM) ............................................. 29-36
30-1 SPI Block Diagram ............................................................................................................... 30-1
30-2 Single-Master/Multi-Slave Configuration ............................................................................ 30-3
30-3 Multimaster Configuration.................................................................................................... 30-5
30-4 SPI Mode Register (SPMODE) ............................................................................................ 30-6
30-5 SPI Transfer Format with SPMODE[CP] = 0....................................................................... 30-7
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Title
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
Freescale Semiconductor