Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 446

Memory Controller
Address
Comparator
Bank Select
MS
Field
15.3 Chip-Select Programming Common to the GPCM and UPM
The GPCM and the UPMs use the memory controller registers as specified in
Section 15.4, "Register Descriptions,"
Base register bank 0–7 register (BR x )
Option register bank 0–7 register (OR x )
Memory status register (MSTAT)
Memory command register (MCR)
Machine A mode register (MAMR)
Machine B mode register (MBMR)
Memory data register (MDR)
Memory address register (MAR)
Memory periodic timer prescaler register (MPTPR)
15-6
Internal/External Memory Access Request Select
Address (A),
Address
Type (AT)
UPMA
Signals
Timing
Generator
Figure 15-4. Basic Memory Controller Operation
for specific register information.
Table 15-1. Memory Controller Register Usage
Register
MPC885 PowerQUICC Family Reference Manual, Rev. 2
UPMB GPCM
Signals
Timing
Generator
MUX
External Signals
Table
Used by the GPCM
√
√
√
15-1. See
Used by a UPM
√
√
√
√
√
√
√
√
√
Freescale Semiconductor