Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 155

Functionality
Integer processor The core implements the following integer instructions:
• Arithmetic instructions
• Compare instructions
• Trap instructions
• Logical instructions
• Rotate and shift instructions
Move to/from Move to/from invalid SPRs in which SPR[0] = 1 invokes the privileged instruction error exception
SPR instructions handler if the processor is in user mode.
Integer arithmetic Attempting to use divw to perform either 0x80000000
instructions rD to 0x80000000 and if Rc =1, the contents of CR0 are LT = 1, GT = 0, and EQ = 0. SO is set to
the correct value.
In the cmpi, cmp, cmpli, and cmpl instructions, the L bit is applicable for 64-bit implementations.
For the MPC885, if L = 1 the instruction form is invalid. The core ignores this bit and, therefore, the
behavior when L = 1 is identical to the valid form instruction with L = 0.
Integer load/store For load with update and store with update instructions where rA = 0, the EA is written into r0. For
with update load with update instructions where rA = rD, rA is boundedly undefined.
instructions
Integer load/ store For these types of instructions, EA must be a multiple of four. If it is not, the system alignment error
multiple handler is invoked. For an lmw instruction (if rA is in the range of registers to be loaded), the
instructions instruction completes normally. rA is then loaded from the memory location as follows:
rA <- MEM(EA+(rA-rD)*4, 4)
Integer load string Load string instructions behave like load multiple instructions with respect to invalid format in which
instructions rA is in the range of registers to be loaded. If rA is in the range, it is updated from memory.
Memory For these instructions, if EA is not a multiple of four, the system alignment error handler is invoked.
synchronization
instructions
Optional No optional instructions are supported.
instructions
Little-endian byte The LSU supports little-endian byte ordering as specified in the UISA. In little-endian mode, trying
ordering to execute an unaligned individual scalar or multiple/string access causes an alignment exception.
Freescale Semiconductor
Table 3-3. UISA-Level Features (continued)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
÷
-1 or <anything>
The MPC8xx Core
÷
0 sets the contents of
3-15