Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 698

SCC HDLC Mode
• Four address comparison registers with mask
• Maintenance of five 16-bit error counters
• Flag/abort/idle generation and detection
• Zero insertion/deletion
• 16- or 32-bit CRC-CCITT generation and checking
• Detection of nonoctet aligned frames
• Detection of frames that are too long
• Programmable flags (0–15) between successive frames
• Automatic retransmission in case of collision
23.2 SCC HDLC Channel Frame Transmission
The HDLC transmitter is designed to work with little or no core intervention. Once enabled by the core, a
transmitter starts sending flags or idles as programmed in the HDLC mode register (PSMR). The HDLC
polls the first BD in the TxBD table. When there is a frame to transmit, the SCC fetches the data from
memory and starts sending the frame after sending the minimum number of flags specified between
frames. When the end of the current buffer is reached and TxBD[L] (last buffer in frame) is set, the CRC
and closing flag are appended. In HDLC mode, the lsb of each octet and the msb of the CRC are sent first.
Figure 23-1 shows a typical HDLC frame.
Opening Flag
8 bits
After a closing flag is sent, the SCC updates the frame status bits of the BD and clears TxBD[R] (buffer
ready). At the end of the current buffer, if TxBD[L] is not set (multiple buffers per frame), only TxBD[R]
is cleared. Before the SCC proceeds to the next TxBD in the table, an interrupt can be issued if TxBD[I]
is set. This interrupt programmability allows the core to intervene after each buffer, after a specific buffer,
or after each frame.
The command can be used to expedite critical data ahead of previously linked buffers or
STOP TRANSMIT
to support efficient error handling. When the SCC receives a
flags instead of the current frame until it receives a
command can be used to insert a high-priority frame without aborting the current one—a
TRANSMIT
graceful-stop-complete event is generated in SCCE[GRA] when the current frame is finished. See
Section 23.6, "SCC HDLC Commands."
23.3 SCC HDLC Channel Frame Reception
The HDLC receiver is designed to work with little or no core intervention to perform address recognition,
CRC checking, and maximum frame length checking. Received frames can be used to implement any
HDLC-based protocol.
23-2
Address Control
16 bits 8 bits
Figure 23-1. HDLC Framing Structure
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Information (Optional)
8 n bits
STOP TRANSMIT
command. The
RESTART TRANSMIT
CRC Closing Flag
16 bits 8 bits
command, it sends idles or
GRACEFUL STOP
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