Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 172

MPC885 Instruction Set
The concept of alignment is also applied more generally to data in memory. For example, a 12-byte data
item is said to be word-aligned if its address is a multiple of four.
Any memory access that crosses an alignment boundary must be broken into multiple discrete accesses.
For the case of string accesses, the hardware makes no attempt to get aligned in an effort to reduce the
number of discrete accesses. (Multi-word accesses are architecturally required to be aligned.) The
resulting performance degradation depends upon how well each individual access behaves with respect to
the memory hierarchy. At a minimum, additional cache access cycles are required. More dramatically, for
the case of access to a noncacheable page, each discrete access involves an individual bus operation which
will reduce the effective bandwidth of the bus.
The frequent use of misaligned accesses is discouraged since they can compromise the overall
performance of the processor.
5.2 Instruction Set Summary
This section describes instructions and addressing modes defined for the MPC885. These instructions are
divided into the following functional categories:
• Integer instructions—These include arithmetic and logical instructions. For more information, see
Section 5.2.4.1, "Integer Instructions."
• Load and store instructions—These include integer load and store instructions only. For more
information, see
• Flow control instructions—These include branching instructions, condition register logical
instructions, and other instructions that affect the instruction flow. For more information, see
Section 5.2.4.3, "Branch and Flow Control Instructions."
• Trap instructions—These instructions test for a specified set of conditions; see
"Trap Instructions,"
• Processor control instructions—These instructions synchronize memory accesses and managing
caches and TLBs. For more information, see Sections 5.2.4.5, 5.2.5.1, and 5.2.6.2.
• Memory synchronization instructions—These instructions are used for memory synchronizing.
See Sections 5.2.4.6 and 5.2.5.2 for more information.
• Memory control instructions—These instructions provide control of caches, and TLBs. For more
information, see Sections 5.2.5.3 and 5.2.6.3.
• System linkage instructions—For more information, see
Instructions."
Note that this grouping of instructions does not necessarily indicate the execution unit that processes a
particular instruction or group of instructions. This information, which is useful in taking full advantage
of the MPC885's parallel instruction execution, is provided in Chapter 8, "Instruction Set," in The
Programming Environments Manual.
Integer instructions operate on word operands. The architecture uses instructions that are four bytes long
and word-aligned. It provides for byte, half word, and word operand loads and stores between memory and
a set of 32 general-purpose registers (GPRs).
5-2
Section 5.2.4.2, "Load and Store Instructions."
for more information.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Section 5.2.4.4,
Section 5.2.6.1, "System Linkage
Freescale Semiconductor