Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 207

Table 6-16. Register Settings After a Data TLB Error Exception (continued)
Register
DSISR 0 0
1 Set if the translation of an attempted access is not found in the translation tables. Otherwise,
cleared
2–3 0
4 Set if the memory access is not permitted by the protection mechanism; otherwise cleared
5 0
6 1 for a store operation; 0 for a load operation.
7–31 0
DAR Set to the EA of the data access that caused the exception.
Some instruction TLB registers are set to the values described in
Execution resumes at offset 0x01400 from the base address indicated by MSR[IP].
6.1.3.6 Debug Exceptions (0x01C00–0x01F00)
A debug exception occurs in response to one of the following conditions:
• When there is an internal breakpoint match (for more details, see
Breakpoints Support.")
• When a peripheral breakpoint request is presented to the exception mechanism
• When the development port request is presented to the exception mechanism
Table 6-17 shows the following register settings:
Register
SRR0 For I-breakpoints, set to the EA of the instruction that caused the exception. For L-breakpoint, set to the
EA of the instruction after the one that caused the exception. For development port maskable request or
a peripheral breakpoint, set to the EA of the instruction that the processor would have executed next if
no exception conditions were present. If the development port request is asserted at reset, the value of
SRR0 is undefined.
SRR1 1–4 0
10–15 0
Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
If the development port request is asserted at reset, the value of SRR1 is undefined.
MSR IP No change
ME No change
LE Copied from the ILE setting of the interrupted process
Other 0
BAR For L-bus breakpoint conditions. Set to the EA of the data access as computed by the instruction that
caused the exception.
DSISR For L-bus breakpoint conditions. Do not change.
DAR For L-bus breakpoint conditions. Do not change.
Freescale Semiconductor
Table 6-17. Register Settings after a Debug Exception
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Setting
Chapter 8, "Memory Management Unit."
Section 53.2, "Watchpoints and
Setting
Exceptions
6-15