Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 752

SCC BISYNC Mode
Table 26-12. SCC BISYNC TxBD Status and Control Field Descriptions (continued)
Bits Name
6 CM Continuous mode
0 Normal operation
1 The CP does not clear R after this BD is closed, so the buffer is resent when the CP next
accesses this BD. However, R is cleared if an error occurs during transmission, regardless of how
CM is set.
7 BR BCS reset. Determines whether transmitter BCS accumulation is reset before sending the data
buffer.
0 BCS accumulation is not reset.
1 BCS accumulation is reset before sending the data buffer.
8 TD Transmit DLE
0 No automatic DLE transmission can occur before the data buffer.
1 The transmitter sends a DLE character before sending the buffer, which saves writing the first
DLE to a separate buffer in transparent mode. See TR for information on control characters.
9 TR Transparent mode
0 The transmitter enters and stays in normal mode after sending the buffer. The transmitter
automatically inserts SYNCs if an underrun condition occurs.
1 The transmitter enters or stays in transparent mode after sending the buffer. It automatically
inserts DLE–SYNC pairs if an underrun occurs (the controller finishes a buffer with L = 0 and the
next BD is not available). It also checks all characters before sending them. If a DLE is detected,
another DLE is sent automatically. Insert a DLE or program the controller to insert one before
each control character. The transmitter calculates the CRC16 BCS even if PSMR[BCS] is
programmed to LRC. Initialize PTCRC to CRC16 before setting TR.
10 B BCS enable
0 The buffer consists of characters that are excluded from BCS accumulation.
1 The buffer consists of characters that are included in BCS accumulation.
11–13 — Reserved, should be cleared.
14 UN Underrun. Set when the BISYNC controller encounters a transmitter underrun error while sending
the associated data buffer. The CPM writes UN after it sends the associated buffer.
15 CT CTS lost. The CP sets CT when CTS is lost during message transmission after it sends the data
buffer.
Data length and buffer pointer fields are described in
Although it is never modified by the CP, data length should be greater than zero. The CPM writes these
fields after it finishes sending the buffer.
26.14 BISYNC Event Register (SCCE)/BISYNC Mask
Register (SCCM)
The BISYNC controller uses the SCC event register (SCCE) to report events recognized by the BISYNC
channel and to generate interrupts. When an event is recognized, the controller sets the corresponding
SCCE bit. Interrupts are enabled by setting, and masked by clearing, the equivalent bits in the BISYNC
mask register (SCCM). SCCE bits are reset by writing ones; writing zeros has no effect. Unmasked bits
must be reset before the CP negates the internal interrupt request signal.
26-14
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Section 21.3, "SCC Buffer Descriptors (BDs)."
Freescale Semiconductor