Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 333

A0–M16
A1–N18
A2–N19
A3–M19
A4–M17
A5–M18
A6–L16
A7–L19
A8–L17
A9–L18
A10–K19
A11–K18
A12–K17
A13–K16
D0–P2
A14–J19
D1–M1
A15–J17
D2–L1
A16–J18
D3–K2
A17–J16
D4–N1
A18–E19
D5–K4
A19–H18
D6–H3
A20–H17
D7–F2
A21–G19
D8–P1
A22–F17
D9–L4
A23–G17
D10–L3
A24–H16
D11–L2
A25–F19
D12–N3
A26–D19
D13–N2
A27–H19
D14–K3
A28–E18
D15–K1
A29–G18
D16–J2
A30–F18
D17–M4
A31–D18
D18–J1
D19–J3
D20–H2
D21–H1
D22–J4
D23–M3
D24–G2
D25–G1
D26–G3
D27–M2
D28–H4
D29–F1
D30–E1
D31–F3
MII1_CRS
T11-1
MII1_COL
MII_MDIO
MII1_TXEN
Freescale Semiconductor
32
G16–1
E17–1
D13–1
C10–1
A13–1
A12–1
C12–1
B12–1
D12–1
B10–1
C7–1
A11–1
32
D11–1
C11–1
B11–1
D10–1
N4,P3–2
P4–1
6
D15–1
B16–1
B18–1
E16–1
C17–1
B19–1
D17,C18,C19,F16–4
B17–1
A18–1
D16, A17–2
B13–1
MPC885
A14–1
C13–1
B3–1
D4–1
B4–1
A3–1
A4–1
D5–1
G4–1
A5–1
C4–1
B7–1
B15–1
C15–1
A2–1
B1, C1–2
F4–1
E3, D2, D1, E2, D3–5
D8–1
C3–1
A9, D9–2
C8–1
U12-1
C9–1
B9–1
P19-1
A10–1
T5-1
A8–1
B8–1
B6, C6–2
D6–1
A6–1
A7–1
C5, B5–2
Figure 12-2. MPC885 Signals and Pin Numbers (Part 2)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
A[0:31]
TSIZ0/REG
TSIZ1
RD/WR
BURST
BDIP/GPL_B5
TS
TA
TEA
BI
IRQ2/RSV
IRQ4/KR/RETRY/SPKROUT
CR/IRQ3
D[0:31]
BR
BG
BB
FRZ/IRQ6
IRQ[0:1]
IRQ7
CS[0:5] – B14,C14,A15,D14,C16,A16
CS6/CE1_B
CS7/CE2_B
WE0/BS_B0/IORD
WE1/BS_B1/IOWR
WE2/BS_B2/PCOE
WE3/BS_B3/PCWE
BS_A[0:3]
GPL_A0/GPL_B0
OE/GPL_A1/GPL_B1
GPL_A[2:3]/GPL_B[2:3]/CS[2:3]
UPWAITA/GPL_A4
UPWAITB/GPL_B4
GPL_A5
PORESET
RSTCONF
HRESET
SRESET
XTAL
EXTAL
CLKOUT
EXTCLK
TEXP
ALE_A
CE1_A
CE2_A,
WAIT_A/ SOC_Split
IP_A[0:1]/ UTPB_Split[0:1]
IP_A2/IOIS16_A/UTPB_Split2
E3–IP_A3/UTPB_Split3
ALE_B/DSCK/AT1
D2–IP_A4/UTPB_Split4
WAIT_B
D1–IP_A5/UTPB_Split5
IP_B[0:1]/WP[0:1]/VFLS[0:1]
E2–IP_A6/UTPB_Split6
IP_B2/IOIS16_B/AT2
D3–IP_A7/UTPB_Split7
IP_B3/WP2/VF2
IP_B4/LWP0/VF0
IP_B5/LWP1/VF1
IP_B6/DSDI/AT0
IP_B7/PTR/AT3
B6-–OP0/UtpClk_Split
C6–OP1
OP2/MODCK1/STS
OP3/MODCK2/DSDO
BADDR30/REG
BADDR[28:29]
External Signals
12-3