Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 656

Serial Communications Controllers
21.2.2 Protocol-Specific Mode Register (PSMR)
The protocol implemented by an SCC is selected by its GSMR_L[MODE]. Each SCC has an additional
protocol-specific mode register (PSMR) for configurations specific to the chosen protocol. The PSMR
fields are described in the specific chapters that describe each protocol. These registers are affected by
HRESET and SRESET.
21.2.3 Data Synchronization Register (DSR)
Each SCC has a data synchronization register (DSR) that specifies the pattern used for frame
synchronization. The programmed value for DSR depends on the protocol:
• UART—DSR is used to configure fractional stop bit transmission.
• BISYNC and transparent—DSR should be programmed with the sync pattern.
• Ethernet—DSR should be programmed with 0xD555.
• HDLC—At reset, DSR defaults to 0x7E7E (two HDLC flags), so it does not need to be written.
This register is affected by HRESET and SRESET.
0
Field
Reset 0 1
R/W
Addr
21.2.4 Transmit-on-Demand Register (TODR)
In normal operation, if no frame is being sent by an SCC, the CP periodically polls the R bit of the next
TxBD to see if a new frame/buffer is requested. Depending on the SCC configuration, this polling occurs
every 8–32 serial Tx clocks. The transmit-on-demand option, selected in the transmit-on-demand register
(TODR) shown in Figure
protocols where maximum interframe gap times are limited by the protocol specification.
0 1
Field TOD
Reset
R/W
Addr
The CP can be configured to begin processing a new frame/buffer without waiting the normal polling time
by setting TODR[TOD] after TxBD[R] is set. Because this feature favors the specified TxBD, it may affect
servicing of the FIFOs of other CPM controllers. Therefore, transmitting on demand should only be used
21-10
SYN2
1 1 1 1 1
0xA2E (DSR2), 0xA4E (DSR3), 0xA6E (DSR4)
Figure 21-4. Data Synchronization Register (DSR)
21-5, shortens the latency of the Tx buffer/frame and is useful in LAN-type
0xA2C (TODR2), 0xA4C (TODR3), 0xA6C (TODR4)
Figure 21-5. Transmit-on-Demand Register (TODR)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Figure 21-4 shows the sync fields.
7 8
0 0 1 1 1
R/W
—
0
R/W
15
SYN1
1 1 1 0
15
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