Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 70

Table
Number
11-1 MPC885 Reset Responses .................................................................................................... 11-1
11-2 Reset Status Register Bit Settings ......................................................................................... 11-5
11-3 Hard Reset Configuration Word Field Descriptions ............................................................. 11-8
12-1 MPC885/MPC880 Signal Descriptions ................................................................................ 12-4
12-2 MPC875/MPC870 Signal Descriptions .............................................................................. 12-26
12-3 Configuration-Dependent Signal Behavior During Reset .................................................. 12-40
12-4 Active Pull-Up Resistors Enabled as Outputs..................................................................... 12-41
12-5 General Signal Behavior During Reset ............................................................................... 12-44
13-1 MPC885 Signal Overview .................................................................................................... 13-3
13-2 Data Bus Requirements for Read Cycles............................................................................ 13-25
13-3 Data Bus Contents for Write Cycles ................................................................................... 13-25
13-4 BURST/TSIZ Encoding ...................................................................................................... 13-30
13-5 Address Types Definition.................................................................................................... 13-31
13-6 Termination Signals Protocol.............................................................................................. 13-41
14-1 The Input Frequency Requirements...................................................................................... 14-4
14-2 Typical System Frequency Generation ................................................................................. 14-6
14-3 Power-On Reset DPLL Configuration .................................................................................. 14-7
14-4 Functionality Summary of the Clocks .................................................................................. 14-8
14-5 PITCLK Configuration at PORESET ................................................................................. 14-14
14-6 TMBCLK Configuration..................................................................................................... 14-15
14-7 MPC885 Modules vs. Power Rails ..................................................................................... 14-16
14-8 SCCR Field Descriptions .................................................................................................... 14-19
14-9 PLPRCR Field Descriptions ............................................................................................... 14-21
14-10 PLPRCR[CSR] and DER[CHSTPE] Bit Combinations ..................................................... 14-23
15-1 Memory Controller Register Usage ...................................................................................... 15-6
15-2 Access Granularities for Predefined Port Sizes .................................................................... 15-7
15-3 BRx Field Descriptions....................................................................................................... 15-10
15-4 ORx Field Descriptions....................................................................................................... 15-12
15-5 MSTAT Field Descriptions ................................................................................................. 15-13
15-6 MxMR Field Descriptions .................................................................................................. 15-14
15-7 MCR Field Descriptions ..................................................................................................... 15-16
15-8 MDR Field Descriptions ..................................................................................................... 15-17
15-9 MAR Field Description....................................................................................................... 15-18
15-10 MPTPR Field Descriptions ................................................................................................. 15-18
15-11 GPCM Strobe Signal Behavior ........................................................................................... 15-19
15-12 Boot Bank Field Values After Reset ................................................................................... 15-30
15-13 UPM Start Address Locations............................................................................................. 15-38
15-14 RAM Word Bit Settings ...................................................................................................... 15-38
15-15 Enabling Byte-Selects ......................................................................................................... 15-43
15-16 GPL_x5 Signal Behavior .................................................................................................... 15-44
15-17 MxMR Loop Field Usage ................................................................................................... 15-45
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Tables
Title
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
Freescale Semiconductor