Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 218

Instruction and Data Caches
The two state bits implement a three-state (modified-valid/unmodified-valid/invalid) protocol. The
MPC885 does not provide support for snooping external bus activity. All coherency between the internal
caches and external agents (memory or I/O devices) must be controlled by software.
The data cache also implements a lock bit for each cache block that allows data to be loaded into the data
cache and locked. The MPC885 supports commands for locking and unlocking individual cache blocks
and for unlocking all the cache blocks at once.
7.3 Cache Control Registers
The MPC885 caches are controlled by programming commands using the cache control registers and by
issuing dedicated cache control instructions. This section describes control of the instruction and data
caches by the cache control registers.
control instructions.
7.3.1 Instruction Cache Control Registers
The MPC885 implements three special purpose registers (SPRs) to control the instruction cache: the
instruction cache control and status register (IC_CST), the instruction cache address register (IC_ADR),
and the instruction cache data port register (IC_DAT). The instruction cache can be disabled, invalidated,
or locked by issuing the appropriate commands to the instruction cache control registers (IC_CST,
IC_ADR, and IC_DAT). In addition, the instruction cache control registers can be used to read the contents
and tags of specific instruction cache blocks.
The mtspr and mfspr instructions access the cache control registers, but they can be accessed only by
supervisor-level programs (that is, when MSR[PR] = 0). Any attempt to access these SPRs with a
user-level program (MSR[PR] = 1) results in a supervisor-level program exception.
The IC_CST register, shown in
0 1
Field IEN —
Reset 0 —
R/W R —
16
Field
Reset
R/W
SPR
Figure 7-3. Instruction Cache Control and Status Register (IC_CST)
7-6
Section 7.4, "Cache Control Instructions,"
Figure 7-3, has an SPR encoding of 560.
3 4 6 7
CMD
—
R/W
MPC885 PowerQUICC Family Reference Manual, Rev. 2
9 10 11
— CCER1 CCER2
— 0 0
— R R
—
—
—
560
describes the cache
12 15
—
—
—
31
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