Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 167

Powerquicc family

Table of Contents

MPC885-Specific SPRs

protection, are described in

are described in

Decimal SPR[5–9] SPR[0–4]

Freescale Semiconductor

list SPRs specific to the MPC885. Debug registers, which have additional

Chapter 53, "System Development and Debugging."

Table 4-9. MPC885-Specific Supervisor-Level SPRs

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Reference/Section

Section 6.1.5, "Recoverability After an

Section 10.4.1, "Internal Memory Map

Section 7.3.1, "Instruction Cache

Control Registers"

Section 7.3.1, "Instruction Cache

Control Registers"

Section 7.3.1, "Instruction Cache

Control Registers"

Section 7.3.2, "Data Cache Control

Section 7.3.2, "Data Cache Control

Section 7.3.2, "Data Cache Control

Section 8.8.1, "IMMU Control Register

Section 8.8.10, "MMU Access

Protection Registers (MI_AP/MD_AP)"

Section 8.8.3, "IMMU/DMMU Effective

Page Number Register (Mx_EPN)"

Section 8.8.4, "IMMU Tablewalk

Control Register (MI_TWC)"

Section 8.8.6, "IMMU Real Page

Number Register (MI_RPN)"

Section 8.8.12.1, "IMMU CAM Entry

Read Register (MI_CAM)"

Section 8.8.12.2, "IMMU RAM Entry

Read Register 0 (MI_RAM0)"

MPC8xx Core Register Set

Supervisor-level registers

Serialize Access

Write (as a store)