Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 570

Communications Processor
18.4 CP Microcode Revision Number
In addition to the microcode routines located in internal ROM, the CP can execute protocol-enhancing
microcode packages from dual-port RAM. The CP writes a part revision number stored in ROM to a
dual-port RAM location called REV_NUM that resides in the miscellaneous parameter RAM. REV_NUM
determines which version of Freescale-supplied microcode package to use; see
1
Offset Name
0x00 REV_NUM
0x02
0x04
0x08 CPMCFG
1
Offset from the base of the miscellaneous parameter area (at offset 0x1CB0 of the dual-port RAM).
For the latest documentation on part/revision numbers and microcode REV_NUMs, see the website at
http://www.freescale.com.
18.5 CPM Configuration Register (CPMCFG)
The CPM Configuration Register (CPMCFG) has been added to enable AAL2 functionality and APC flux
compensation. In the future, this register may be used for additional purposes.
CPMCFG register.
Bit
0
Field
Reset
R/W
Addr
Bit
16 17
Field AAL2
Reset 0
R/W
Addr
18-4
Table 18-2. CP Microcode Revision Number
Width
Half-word Microcode revision number
— Half-word Reserved
— Word Reserved
Word CPM Configuration Register
DPRAMbase + 0x1CB8
DPRAMbase + 0x1CBA
Figure 18-2. CPM Configuration Register (CPMCFG)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
—
—
R/W
—
—
R/W
Table 18-2.
Figure 18-2 shows the
15
30 31
APC
0
Freescale Semiconductor