Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 660

Serial Communications Controllers
Table 21-5. SCC Parameter RAM Map for All Protocols (continued)
1
Offset Name Width
0x06 MRBLR Hword
0x08 RSTATE
0x0C RIP
0x10 RBPTR Hword
0x12 RCOUNT Hword
0x14 RTEMP
0x18 TSTATE
0x1C TIP
0x20 TBPTR Hword
0x22 TCOUNT Hword
0x24 TTEMP
0x28 RCRC
0x2C TCRC
0x30
1
From SCC base. SCC base = IMMR + 0x3D00 (SCC2) or 0x3E00 (SCC3) or 0x3F00 (SCC4)
2
These parameters need not be accessed for normal operation but may be helpful for debugging.
3
For CP use only
21-14
Maximum receive buffer length. Defines the maximum number of bytes the CP writes
to a receive buffer before it goes to the next buffer. The CP can write fewer bytes than
MRBLR if a condition such as an error or end-of-frame occurs. It never writes more
bytes than the MRBLR value. Therefore, user-supplied buffers should be no smaller
than MRBLR. MRBLR should be greater than zero for all modes. It should be a
multiple of 4 for Ethernet and HDLC modes, and in totally transparent mode unless
the Rx FIFO is 8-bits wide (GSMR_H[RFW] = 1).
Note: Although MRBLR is not intended to be changed while the SCC is operating, it
can be changed dynamically in a single-cycle, 16-bit move (not two 8-bit
cycles). Changing MRBLR has no immediate effect. To guarantee the exact Rx
BD on which the change occurs, change MRBLR only while the receiver is
disabled.
Transmit buffer length is programmed in TxBD[Data Length] and is not affected by
MRBLR.
3
Word Rx internal state
Word Rx internal buffer pointer
SDMA channels to show the next address in the buffer to be accessed.
Current RxBD pointer. Points to the current BD being processed or to the next BD
the receiver uses when it is idling. After reset or when the end of the BD table is
reached, the CP initializes RBPTR to the value in the RBASE. Although most
applications do not need to write RBPTR, it can be modified when the receiver is
disabled or when no Rx buffer is in use.
Rx internal byte count
with MRBLR and decremented with each byte written by the supporting SDMA
channel.
3
Word Rx temp
3
Word Tx internal state
Word Tx internal buffer pointer
SDMA channels to show the next address in the buffer to be accessed.
Current TxBD pointer. Points to the current BD being processed or to the next BD the
transmitter uses when it is idling. After reset or when the end of the BD table is
reached, the CP initializes TBPTR to the value in the TBASE. Although most
applications do not need to write TBPTR, it can be modified when the transmitter is
disabled or when no Tx buffer is in use (after a
command is issued and the frame completes its transmission).
TRANSMIT
Tx internal byte count
decremented with each byte read by the supporting SDMA channel.
3
Word Tx temp
2
Word Temp receive CRC
2
Word Temp transmit CRC
Protocol-specific area. (The size of this area depends on the protocol chosen.)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
2
. The Rx and Tx internal buffer pointers are updated by the
2
. The Rx internal byte count is a down-count value initialized
2
. The Rx and Tx internal buffer pointers are updated by the
STOP TRANSMIT
2
. A down-count value initialized with TxBD[Data Length] and
or
GRACEFUL STOP
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