Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 187

The functions performed by the sync instruction normally take a significant amount of time to complete;
as a result, frequent use of this instruction may adversely affect performance. In addition, the number of
cycles required to complete a sync instruction depends on system parameters and on the processor's state
when the instruction is issued.
The proper paired use of the lwarx and stwcx. instructions allows programmers to emulate common
semaphore operations such as "test and set," "compare and swap," "exchange memory," and "fetch and
add." Examples of these semaphore operations can be found in Appendix E, "Synchronization
Programming Examples," in the Programming Environments Manual. The lwarx instruction must be
paired with an stwcx. instruction with the same effective address used for both instructions of the pair.
Note that the reservation granularity is 16 bytes.
The lwarx and stwcx. instructions are implemented according to the PowerPC architecture requirements.
The concept behind the use of the lwarx and stwcx. instructions is that a processor may load a semaphore
from memory, compute a result based on the value of the semaphore, and conditionally store it back to the
same location (only if that location has not been modified since it was first read), and determine if the store
was successful. The conditional store is performed based upon the existence of a reservation established
by the preceding lwarx instruction. If the reservation exists when the store is executed, the store is
performed and a bit is set in the CR. If the reservation does not exist when the store is executed, the target
memory location is not modified and a bit is cleared in the CR.
If the store was successful, the sequence of instructions from the read of the semaphore to the store that
updated the semaphore appear to have been executed atomically (that is, no other processor or mechanism
modified the semaphore location between the read and the update), thus providing the equivalent of a real
atomic operation. However, in reality, other processors may have read from the location during this
operation. In the MPC885, the reservations are made on behalf of aligned 16-byte sections of the memory
address space.
The lwarx and stwcx. instructions require the EA to be aligned. Exception handling software should not
attempt to emulate a misaligned lwarx or stwcx. instruction, because there is no correct way to define the
address associated with the reservation.
In general, the lwarx and stwcx. instructions should be used only in system programs, which can be
invoked by application programs as needed.
At most, one reservation exists simultaneously on any processor. The address associated with the
reservation can be changed by a subsequent lwarx instruction. The conditional store is performed based
upon the existence of a reservation established by the preceding lwarx, regardless of whether the address
generated by the lwarx matches that generated by the stwcx. instruction. A reservation held by the
processor is cleared by one of the following:
• Executing an stwcx. instruction to any address
• Attempt by another device to modify a location in the reservation granularity (16 bytes)
In write-through mode, lwarx and stwcx. do not cause a DSI exception.
The sync instruction guarantees that previously fetched instructions finish before any subsequent
instructions are dispatched to the execution units. It does not affect fetching; instructions continue to be
fetched up to the instruction queue limit, but dispatch stalls until the sync finishes.
Freescale Semiconductor
MPC885 PowerQUICC Family Reference Manual, Rev. 2
MPC885 Instruction Set
5-17