Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 176

MPC885 Instruction Set
5.2.2.3 Synchronization
The synchronization described in this section refers to the state of the processor that is performing the
synchronization.
5.2.2.3.1 Context Synchronization
The System Call (sc) and Return from Interrupt (rfi) instructions perform context synchronization by
allowing previously issued instructions to complete before performing a change in context. Execution of
one of these instructions ensures the following:
• No higher priority exception exists (sc).
• All previous instructions have completed to a point where they can no longer cause an exception.
• Previous instructions complete execution in the context (privilege, protection, and address
translation) under which they were issued.
• The instructions following the sc or rfi instruction execute in the context established by these
instructions.
5.2.2.3.2 Execution Synchronization
An instruction is execution synchronizing if all previously initiated instructions appear to have completed
before the instruction is initiated or, in the case of the Synchronize (sync) and Instruction Synchronize
(isync) instructions, before the instruction completes. For example, the Move to Machine State Register
(mtmsr) instruction is execution synchronizing. It ensures that all preceding instructions have completed
execution and will not cause an exception before the instruction executes, but does not ensure subsequent
instructions execute in the newly established environment. For example, if the mtmsr sets the MSR[PR]
bit, unless an isync immediately follows the mtmsr instruction, a privileged instruction could be executed
or privileged access could be performed without causing an exception even though the MSR[PR] bit
indicates user mode.
5.2.2.3.3 Instruction-Related Exceptions
There are two kinds of exceptions in the MPC885—those caused directly by the execution of an instruction
and those caused by an asynchronous event. Either may cause components of the system software to be
invoked.
Exceptions can be caused directly by the execution of an instruction as follows:
• An attempt to execute an illegal instruction causes the illegal instruction (program exception)
handler to be invoked. An attempt by a user-level program to execute the supervisor-level
instructions listed below causes the privileged instruction (program exception) handler to be
invoked. The MPC885 provides the following supervisor-level instructions—dcbi, mfmsr, mfspr,
mtmsr, mtspr, rfi, tlbie, and tlbsync. Note that the privilege level of the mfspr and mtspr
instructions depends on the SPR encoding.
• An attempt to access memory that is not available (page fault) causes the ISI exception
handler to be invoked.
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MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor