Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 703

Error
Nonoctet The channel writes the received data to the buffer, closes the buffer, sets RxBD[NO], and generates
Aligned Frame a maskable RXF interrupt. CRC error status should be disregarded on nonoctet frames. After a
nonoctet aligned frame is received, the receiver enters hunt mode. An immediate back-to-back
frame is still received. The nonoctet data may be derived from the last word in the buffer as follows:
msb
Note that if buffer swapping is used (RFCR[BO] = 0b0x), the figure above refers to the last byte,
rather than the last word, of the buffer. The lsb of each octet is sent first while the msb of the CRC
is sent first.
CRC The channel writes the received CRC to the buffer, closes the buffer, sets RxBD[CR], generates a
maskable RXF interrupt, and increments the CRC error counter CRCEC. After receiving a frame
with a CRC error, the receiver enters hunt mode. An immediate back-to-back frame is still received.
CRC checking cannot be disabled, but the CRC error can be ignored if checking is not required.
23.8 HDLC Mode Register (PSMR)
The protocol-specific mode register (PSMR), shown in
0
Field NOF
Reset
R/W
Addr
Table 23-6 describes PSMR HDLC fields.
Bits Name
0-3 NOF Number of flags. Minimum number of flags between or before frames. If NOF = 0b0000, no flags are
inserted between frames and the closing flag of one frame is followed by the opening flag of the next
frame in the case of back-to-back frames. NOF can be modified on-the-fly.
4–5 CRC CRC selection.
00 16-bit CCITT-CRC (HDLC). X16 + X12 + X5 + 1.
x1 Reserved.
10 32-bit CCITT-CRC (Ethernet and HDLC). X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +
X8 + X7 + X5 + X4 + X2 + X1 +1.
Freescale Semiconductor
Table 23-5. Receive Errors (continued)
Valid Data
3 4 5 6
CRC RTE
0xA28 (PSMR2), 0xA48 (PSMR3), 0xA68 (PSMR4)
Figure 23-3. HDLC Mode Register (PSMR)
Table 23-6. PSMR HDLC Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
1 0
Nonvalid Data
Figure 23-3, functions as the HDLC mode register.
7 8 9 10 11
— FSE DRT BUS BRM MFF
0
R/W
Description
SCC HDLC Mode
lsb
0
12 13 15
—
23-7