Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 219

Table 7-2 describes the bits of the IC_CST register.
Table 7-2. Instruction Cache Control and Status Register—IC_CST
Bits Name
0 IEN Instruction cache enable status
0 The instruction cache is disabled.
1 The instruction cache is enabled.
Note that this is a read-only bit. Any attempt to write to it is ignored.
1–3 — Reserved
4–6 CMD Instruction cache command
000 Reserved
001 Cache enable
010 Cache disable
011 Load-and-lock cache block
100 Unlock cache block
101 Unlock all
110 Invalidate all
111 Reserved
Note that reading these bits always returns 0b000.
7–9 — Reserved
10 CCER1 Instruction cache error type 1—bus error during an IC_CST load & load cache block command
0 No error detected
1 Error detected
Note that this is a read-only, sticky bit, set only by the MPC885 when an error is detected.
Reading this bit clears it.
11 CCER2 Instruction cache error type 2—no unlocked way available for an IC_CST load-and-lock
cache block command
0 No error detected
1 Error detected
Note that this is a read-only, sticky bit, set only by the MPC885 when an error is detected.
Reading this bit clears it.
12–31 — Reserved
The IC_ADR register, shown in
0
Field
Reset
R/W
SPR
Freescale Semiconductor
Figure 7-4, has an SPR encoding of 561.
Figure 7-4. Instruction Cache Address Register (IC_ADR)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
ADR
—
R/W
561
Instruction and Data Caches
31
7-7