Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 303

10.5.4.1 SIU Interrupt Pending Register (SIPEND)
SIU interrupt pending register (SIPEND) bits, shown in
This register is affected by HRESET and SRESET.
0 1 2
Field IRQ0 LVL0 IRQ1 LVL1 IRQ2 LVL2 IRQ3 LVL3 IRQ4 LVL4
Reset
R/W
Addr
16
Field
Reset
R/W
Addr
Table 10-9 describes SIPEND fields.
Bits Name
0, 2, 4, IRQ n Interrupt request 0–7. Indicate whether an edge-triggered interrupt is pending.
6, 8, 12, 0 The appropriate interrupt is not pending.
14 1 The appropriate interrupt is pending.
10 — Reserved
LVL n
1, 3, 5, Level 0–7. When set, these bits indicate a pending level interrupt of corresponding value.
7, 9, 11, 0 The appropriate interrupt is not pending.
13, 15 1 The appropriate interrupt is pending.
16–31 — Reserved, should be cleared.
The LVL[0–7] bits are associated with internal exceptions, and when set indicate that an interrupt service
is requested if they are not masked by the corresponding SIMASK bit. These bits reflect the status of the
internal requesting device and are cleared when the appropriate actions are software-initiated in the device.
Writing to LVLn bits has no effect.
The IRQ[0–7] bits are associated with the IRQ[0:7] signals, and their function depends on the sensitivity
defined for them in SIEL; see
• When an IRQ pin is defined as a level interrupt (SIEL[EDn] = 0), the corresponding IRQ bit
behaves like an LVL bit.
• If an IRQ pin is defined as an edge interrupt (SIEL[EDn] = 1), the corresponding bit being set
indicates that a falling edge was detected on the line and are reset by writing ones to them.
Note that IRQ0 can be masked in only a very limited sense. If SIEL[ED0] = 1, edge-sensitive, and
SIPEND[IRQ0] is not cleared in the interrupt service routine, further assertions of IRQ0 are masked.
Freescale Semiconductor
3 4 5 6
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x010
xxxx_xxxx_xxxx_xxxx
(IMMR & 0xFFFF0000) + 0x012
Figure 10-10. SIU Interrupt Pending Register (SIPEND)
Table 10-9. SIPEND Field Descriptions
Section 10.5.4.3, "SIU Interrupt Edge/Level Register (SIEL)."
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Figure 10-10, correspond to interrupt requests.
7 8 9 10 11
— LVL5 IRQ6 LVL6 IRQ7 LVL7
R/W
—
R/W
Description
System Interface Unit
12 13 14 15
31
10-15