Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 395

Bus Request (BR)
Receives Bus Grant (BG) from arbiter
Asserts Bus Busy (BB) if no other master is driving
Asserts Transfer Start (TS)
Drives address and attributes
Drives BURST asserted
Asserts burst data in progress (BDIP)
Negates Burst Data in Progress (BDIP)
Stops driving data
Freescale Semiconductor
MASTER
Drives data
Drives data
Drives data
Drives data
Figure 13-16. Basic Flow of a Burst Write Cycle
MPC885 PowerQUICC Family Reference Manual, Rev. 2
SLAVE
Receives address
Asserts Transfer Acknowledge (TA)
No
BDIP asserted
?
Yes
Asserts Transfer Acknowledge (TA)
No
BDIP asserted
?
Yes
Asserts Transfer Acknowledge (TA)
No
BDIP asserted
?
Yes
Asserts Transfer Acknowledge (TA)
No
BDIP asserted
?
Yes
External Bus Interface
Don't sample
next data
Don't sample
next data
Don't sample
next data
Don't sample
next data
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