Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 470

Memory Controller
Register Field Name
BR0
OR0
CSNT
SETA
TRLX
EHTR
15.5.3 External Asynchronous Master Support
Figure 15-29 shows the basic interface between an asynchronous external master and the GPCM to allow
connection to static RAM.
Figure 15-29. Asynchronous External Master Configuration for
Figure 15-30 shows the timing for TRLX = 0 when an external asynchronous master accesses SRAM. TA,
WE, and OE remain asserted until the external master negates AS, at which point they deassert
asynchronously.
15-30
Table 15-12. Boot Bank Field Values After Reset
PS From hard reset configuration word
— 0
WP 0
MS 00
V From hard reset configuration word
AM All zeros
ATM 000
1
ACS 11
SCY 1111
0
1
0
ASYNCHRONOUS EXTERNAL MASTER
TA
MPC885
TA
AS
Address
CS
OE
WE
Data
GPCM-Handled Memory Devices
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Value
AS Address Data
MEMORY
Address
CE
OE
W
Data
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