Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 281

Powerquicc family

Table of Contents

Branch Prediction

In this example, the blt instruction is dependent on the cmpi instruction. Nevertheless, the BPU predicts

the correct path and allows an overlap of its bubbles with those of lwz. When cmpi writes back, the BPU

reevaluates the decision. If the prediction is correct, no more action is taken and execution continues.

Instructions on the predicted path cannot be dispatched before the condition is resolved.

Read + Execute

L Address Drive

Load Writeback

Branch Decode

Branch Execute

Branch Final

Instruction Timing List

summarizes instruction execution timings in terms of latency and blockage of the appropriate

execution unit. A serializing instruction blocks all execution units.

Instructions

Branch: b, ba, bl, bla, bc, bca, bcl, bcla, bclr, bclrl,

bcctr, bcctl

System call: sc, rfi

CR logical: crand, crxor, cror, crnand, crnor, crandc,

creqv, crorc, mcrf

Freescale Semiconductor

Figure 9-8. Branch Prediction Timing

Table 9-1. Instruction Execution Timing

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Serialize + 2

Instruction Execution Timing