Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 742

Powerquicc family

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SCC BISYNC Mode

From SCC base. SCC base = IMMR + 0x3D00 (SCC2) or 0x3E00 (SCC3) or 0x3F00 (SCC4)

The SYN1–SYN2 synchronization characters are programmed in the DSR (see

Synchronization Register

modes; receive and transmit errors are reported through their respective BDs. Line status is reflected on

port C pins and a maskable interrupt is generated when the status changes. There are two basic ways to

handle BISYNC channels:

The controller can inspect data on a per-byte basis and interrupt the core each time a byte is

The controller can be programmed so software handles the first two or three bytes. The controller

directly handles subsequent data without interrupting the core.

Table 26-1. SCC BISYNC Parameter RAM Memory Map

Hword BISYNC DLE register. Contains the value to be sent as the first byte of a

DLE–SYNC pair and stripped on receive. See

Hword Control character 1–8. These values represent control characters that the

BISYNC controller recognizes. See

Character Recognition."

Hword Receive control character mask. Masks CHARACTER n comparison so control

character classes can be defined. Setting a bit enables and clearing a bit masks

comparison. See

Section 26.6, "SCC BISYNC Control Character Recognition."

(DSR)"). The BISYNC controller uses the same basic data structure as other

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Section 26.8, "SCC BISYNC DLE

Section 26.6, "SCC BISYNC Control

Section 21.2.3, "Data

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