Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 211

Time Point
A
B
C Start fetch handler
D (at least 3
clocks after B)
E
Note: The following are time point explanations.
A—At time point A the excepting instruction dispatches and begins executing. Previously dispatched instructions are
proceeding through the pipeline.
B—The excepting instruction has executed and reached CQ0; previous instructions have finished execution without generating
exceptions. The exception is recognized and between B and D (between 3 and 10 cycles) the effects of any instructions after
the one that generated the interrupt are cancelled and the instructions are flushed. If the instruction had not generated an
exception, it would have been retired.
C—The core fetches the first instructions of the exception handler if the exception handler is external. It is 5 cycles if it is in the
instruction cache and no-show mode is on.
D—All state has been restored. During the interval between D and E, the machine is saving context information in the SRR0
and SRR1 registers, disabling exceptions, placing the machine in privileged mode, and fetching instructions of the exception
handler. The interval between D and E requires at least one clock. The time between C and E depends on the memory system
and the time it takes to fetch the first instruction of the exception handler. For full completion queue restore time, it is no less
than two clocks.
E—The MSR and instruction pointer of the executing process have been saved and control has been transferred to the
exception handler routine. Exception handler instructions that have been fetched can be dispatched.
6.1.7 Partially Completed Instructions
Partially completed instructions can be reexecuted after the exception is handled. This precise exception
model can simplify exception processing because software does not have to save the machine's internal
states, unwind the pipelines, or cleanly terminate the faulting instruction stream and reverse the process to
resume execution of the faulting stream.
Exception Type
Hard reset (caused by HRESET or SRESET)
System reset
Machine check
1
TLB miss/error
Other noninstruction-related exceptions
Alignment
Privileged instruction
Freescale Semiconductor
Table 6-19. Exception Latency
Fetch Issue
Faulting instruction issue
First instruction of handler
dispatched
Table 6-20. Before and After Exceptions
Instruction Type
Any
Any
Any
Any
Any
Load/store
Any privileged
instruction
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Instruction Complete
Instruction complete and all
previous instructions complete
Before/After Contents of SRR0
NA Undefined
Before Next instruction to execute
Before Faulting instruction
Before Faulting fetch or load/store
Before Next instruction to execute
Before Faulting instruction
Before Faulting instruction
Exceptions
Kill Pipeline
Kill pipeline
6-19