Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 913

Powerquicc family

Table of Contents

The BUSY Signal

In pulsed handshake mode, the PIP receiver can generate an additional BUSY handshake signal that is

useful when implementing a Centronics receiver interface. The BUSY output is used to indicate a transfer

in progress; the PIP receiver asserts BUSY as soon as data is latched into the PIP data register.

Figure 33-13

shows the pulsed handshake timing including a BUSY signal.

The timing of BUSY negation can be programmed relative to ACK; see

Handshake Timing."

Core software can also control the assertion and negation of BUSY via PIPC; see

Section 33.4.1, "PIP Configuration Register (PIPC)."

BUSY is multiplexed onto PB31. It can be used only with the 8-bit PIP interface (not the 16-bit interface).

A PIP transmitter can be configured to ignore BUSY or suspend assertion of the STB output until the

receiver BUSY signal is negated.

Pulsed Handshake Timing

When the PIP is under CP control, the pulsed-handshake timing parameters are governed by

PTPR[TPARn] fields, which define an interval from 1 to 256 system clocks; see

Timing Parameters Register (PTPR)."

Figure 33-14

shows how the timing parameter TPAR1 governs the setup time and TPAR2 defines the pulse

width of STB of a PIP transmitter using pulsed handshake mode timing.

Freescale Semiconductor

Figure 33-13. Pulsed Handshake BUSY Signal

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Parallel Interface Port (PIP)

Section 33.7.2.2, "Pulsed

Section 33.4.4, "PIP