Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 475

15.6.3 Control Signal Generation Timing
Fields in the RAM word specify the value of the various external signals at each clock edge. The signal
timing generator causes external signals to behave according to the timing specified in the current RAM
word. Figure 15-34 and Figure 15-35
clock phases shown reflect timing windows during which generated signals can change state.
shows the clock scheme selected when the SCCR[EBDF] = 00; CLKOUT is the same as system clock.
System Clock
CLKOUT
GCLK1_50
GCLK2_50
Clock Phase
Figure 15-34. UPM Clock Scheme One (Division Factor = 1)
In Figure 15-35, if SCCR[EBDF] = 01, CLKOUT equals the system clock divided by 2. In this scheme
GCLK1_50 does not have a 50% duty cycle.
System Clock
CLKOUT
GCLK1_50
GCLK2_50
Clock Phase
Figure 15-35. UPM Clock Scheme Two (Division Factor = 2)
The state of the external signals may change (if specified in the RAM array) at any edge of GCLK1_50
and GCLK2_50, plus a propagation delay, specified in the MPC885 Hardware Specifications. Note
however that only the CS signal corresponding to the currently accessed bank will be manipulated by the
UPM pattern when it runs. The BS signal assertion and negation timing is also specified for each cycle in
the RAM word, but which of the four BS signals will be manipulated by the being run depends on the port
size of the specified bank, the external address accessed, and the value of TSIZn. The GPL lines toggle as
programmed for any access that initiates a particular pattern, but resolution of control is slightly more
limited.
Freescale Semiconductor
show the clock schemes of the UPMs in the memory controller. The
1 2 3
RAM Word
1 2 3
RAM Word
MPC885 PowerQUICC Family Reference Manual, Rev. 2
4 1 2
RAM Word
4 1 2
RAM Word
Memory Controller
Figure 15-34
3 4
3 4
15-35