Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 813

Figure 29-10 shows an example of the timing of various events in the SMCE.
Characters
Received by SMC UART
Time
RXD Line Idle
SMC UART SMCE
Events
NOTES:
1. The first RX event assumes receive buffers are 6 bytes each.
2. The second RX event position is programmable based on the MAX_IDL value.
3. The BRK event occurs after the first break character is received.
Characters
Transmitted by SMC UART
TXD Line Idle
SMC UART SMCE
Events
NOTES:
1. The TX event assumes all seven characters were put into a single buffer, and the TX event occurred when
character was written to the SMC transmit FIFO.
29.3.13 SMC UART Controller Programming Example
The following initialization sequence assumes 9,600 baud, 8 data bits, no parity, and 1 stop bit in a 25-MHz
system. BRG1 and SMC1 are used.
1. Configure the port B pins to enable SMTXD1 and SMRXD1. Set PBPAR[24, 25] then clear
PBDIR[24, 25] and PBODR[24, 25].
2. Configure the BRG1. Write BRGC1 with 0x01_0144. The DIV16 bit is not used and the divider is
162 (decimal). The resulting BRG1 clock is 16× the preferred bit rate.
3. Connect BRG1 to SMC1 using the SI. Clear SIMODE[SMC1, SMC1CS].
4. Assuming one RxBD at the beginning of dual-port RAM followed by one TxBD, write RBASE
with 0x0000 and TBASE with 0x0008.
5. Write 0x0091 to CPCR to execute the
6. Initialize the SDMA configuration register (SDCR) to 0x0001.
7. Write RFCR and TFCR with 0x10 for normal operation.
8. Write MRBLR with the maximum number of bytes per receive buffer. Assume 16 bytes, so
MRBLR = 0x0010.
9. Write MAX_IDL with 0x0000 in the SMC UART-specific parameter RAM to disable the
MAX_IDL functionality for this example.
10. Clear BRKLN and BRKEC in the SMC UART-specific parameter RAM.
Freescale Semiconductor
10 Characters
RX
7 Characters
Figure 29-10. SMC UART Interrupts Example
INIT RX AND TX PARAMETERS
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Serial Management Controllers (SMCs)
Line Idle
RX
Line Idle
TX
command.
Break
BRK BRKE
29-19