Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 941

Bits
0
Field
Reset
R/W
Addr
Bits
16 17
Field D16 D17 D18
Reset
R/W R/W R/W R/W
Addr
Table 34-24 describes PEDAT bits.
Bits Name
0–13 — Reserved
D n
14–31 Contains the data on the corresponding signal
34.6.1.3 Port E Data Direction Register (PEDIR)
Port E data direction register (PEDIR) bits configure port E signals as general-purpose inputs or outputs.
If a signal is not programmed for general-purpose I/O, PEDIR, depending also on PESO register, selects
the peripheral function to be performed.
m
0
Field
Reset — —
R/W
Addr
16 17
Field DR16 DR17 DR18 DR19 DR20 DR21 DR22 DR23 DR24 DR25 DR26 DR27 DR28 DR29 DR30 DR31
Reset 0 0
R/W R/W R/W R/W
Addr
Freescale Semiconductor
18 19 20 21 22
D19 D20 D21 D22
R/W R/W R/W R/W
Figure 34-20. Port E Data Register (PEDAT)
Table 34-24. PEDAT Bit Descriptions
— — — — —
18 19 20 21 22
0 0 0 0 0
R/W R/W R/W R/W
Figure 34-21. Port E Data Direction Register (PEDIR)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
—
Undefined
—
0xAD8
23 24 25 26
D23 D24 D25 D26
Undefined
R/W R/W R/W R/W
0xADA
Description
—
— — — —
—
0xAC8
23 24 25 26
0 0 0 0
R/W R/W R/W R/W
0xACA
Parallel I/O Ports
13 14 15
D14 D15
R/W R/W
27 28 29 30 31
D27 D28 D29 D30 D31
R/W R/W R/W R/W R/W
13 14 15
DR14 DR15
— — — 0 0
R/W R/W
27 28 29 30 31
0 0 0 0 0
R/W R/W R/W R/W R/W
34-23