Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 952

CPM Interrupt Controller
Bits Name
24 IEN Interrupt enable. Master enable for CPM interrupts.
0 CPM interrupts are disabled
1 CPM interrupts are enabled
25–30 — Reserved
31 SPS Spread priority scheme. Selects the relative priority scheme; cannot be changed dynamically.
0 Grouped. The USB and SCCs are grouped by priority at the top of the table.
1 Spread. The USB and SCCs are spread by priority in the table.
1
Note: Do not program the USB or the same SCC to more than one priority position (a, b, c, or d). These bits can be
changed dynamically. Also, the bit pattern 11 should be used for the combination that is not implemented.
35.5.2 CPM Interrupt Pending Register (CIPR)
Each bit in the read/write CPM interrupt pending register (CIPR) corresponds to a CPM interrupt source.
The CPIC sets the appropriate CIPR bit when a CPM interrupt is received. Names and placement of bits,
shown in Figure 35-4, are identical in the CIPR, CIMR, and CISR, and they follow the priorities described
in Table 35-1. These registers are affected by HRESET and SRESET.
0 1 2
Field PC15 USB SCC2 SCC3 SCC4 PC14 TIMER1 PC13
Reset
R/W
Addr
16 17 18
Field PC11 PC10 — TIMER3 PC9
Reset
R/W
Addr
Figure 35-4. CPM Interrupt Pending/Mask/In-Service Registers (CIPR/CIMR/CISR)
In a vectored interrupt scheme, the CPIC clears the appropriate CIPR bit when the core acknowledges the
interrupt by setting CIVR[IACK]. The vector number corresponding to the CPM interrupt source is then
available for the core in CIVR[VN]. However, the CIPR bit is not cleared if an event register exists for that
interrupt source. Event registers exist only for interrupt sources with multiple interrupt events (for
example, the USB and SCCs).
In a polled interrupt scheme, the user must periodically read the CIPR. To avoid losing subsequent events
from the same interrupt source, acknowledge an interrupt before actually handling it in the service routine.
Acknowledge interrupts from port C by clearing the CIPR bit directly (by writing ones). For all other
interrupt sources, however, clear the unmasked event register bits instead, thus causing the CIPR bit to be
cleared.
35-8
Table 35-3. CICR Field Descriptions (continued)
3 4 5 6 7
0000_0000_0000_0000
0x944 (CIPR), 0x948 (CIMR), 0x94C (CISR)
19 20 21 22 23
PC8 PC7 —
0000_0000_0000_0000
0x946 (CIPR), 0x94A (CIMR), 0x94E (CISR)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
8 9 10 11
PC12 SDMA IDMA1 IDMA2
R/W
24 25 26 27
TIMER4 PC6 SPI SMC1
R/W
12 13 14 15
— TIMER2 RTT I2C
28 29 30 31
SMC2/PIP PC5 PC4 —
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