Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 279

GCLK1
Fetch
Decode
Read + Execute
Writeback
L Address Drive
L Data
Cache Address
Load Writeback
E Address
E Data
9.1.4 Fastest External Load (Data Cache Miss)
Figure 9-5 shows a sub instruction dependent on the value read by the load. It causes three bubbles in the
execution stream. Assuming SCCR[EBDF] = 00, the external clock (CLKOUT) is shifted 90° from the
internal clock (GCLK1).
lwz r12,64 (SP)
sub r3,r12,3
addic r4,r14,1
GCLK1
Fetch
Decode
Read + Execute
Writeback
L Address Drive
L Data
Cache Address
Load Writeback
E Address
E Data
9.1.5 A Full Completion Queue
Figure 9-6 shows stalls due to a full CQ. Here, the CQ is full from executing sub, addic, and and. It takes
one more bubble from the load writeback to allow further issue while the CQ retires sub, addic, and and.
lwz r12,64 (SP)
sub r5,r5,3
addic r4,r14,1
and r3,r4.r5
Freescale Semiconductor
lwz sub cror
load sub
load
lwz
Figure 9-4. Private Writeback Bus Load Timing
lwz sub addic
lwz sub
lwz
lwz
Figure 9-5. External Load Timing
MPC885 PowerQUICC Family Reference Manual, Rev. 2
and xor
cror
and
sub cror and
cror
sub
lwz
lwz
Bubble Bubble Bubble
lwz
lwz
Instruction Execution Timing
ori
xor ori
xor ori
and xor ori
lwz
lwz
lwz
Bubble sub
sub
lwz
lwz
lwz
9-3