Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 732

SCC Asynchronous HDLC Mode and IrDA
Table 25-8 describes asynchronous HDLC SCCS fields.
Table 25-8. Asynchronous HDLC SCCS Field Descriptions
Bits Name
0–6 — Reserved, should be cleared.
7 ID Idle status. Set when RXD has been a logic one for at least a full character time.
0 The line is not idle.
1 The line is idle.
25.13.3 Asynchronous HDLC Mode Register (PSMR)
When the SCC is in asynchronous HDLC mode, the PSMR, shown in
asynchronous HDLC mode register.
0 1
Field FLC —
Reset
R/W
Addr
Table 25-9 describes PSMR fields.
Bits Name
0 FLC Flow control
0 Normal operation.
1 Asynchronous flow control. When CTS is negated, the transmitter stops at the end of the current
character. If CTS remains negated past the middle of the character, the next full character is sent
before transmission stops. If CTS is reasserted, transmission resumes from where it stopped and
no CTS lost error is reported. Only idle characters are sent while CTS is negated.
1 — Reserved, should be cleared.
2–3 CHLN Character length. On other protocols CHLN is the number of data bits in a character. For
asynchronous HDLC mode and IrDA modes, CHLN must be set to 0b11 (indicating a character
length of 8 bits).
4–15 — Reserved, should be cleared.
25.14 SCC Asynchronous HDLC RxBDs
The CPM uses the RxBD, shown in
process is shown in Figure 23-5
25-10
2 3 4
CHLN
0xA28 (PSMR2), 0xA48 (PSMR3), 0xA68 (PSMR4)
Figure 25-6. Asynchronous HDLC Mode Register (PSMR)
Table 25-9. PSMR Field Descriptions
Figure 25-7, to report on received data. An example of the RxBD
of Section 23.9, "SCC HDLC Receive Buffer Descriptor (RxBD)."
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Figure 25-6, acts as the
—
0
R/W
Description
15
Freescale Semiconductor