Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 904

Parallel Interface Port (PIP)
Table 33-5. Control Character Table, RCCM, and RCCR Descriptions (continued)
1
Offset Bits
0x3E 0–7
8–15
1
Offset from PIP base address. PIP base = IMMR + 0x3F80 (SMC2).
33.4 The PIP Registers
The PIP registers include one configuration register (PIPC), and an event register (PIPE) with its
corresponding mask register (PIPM). A timing parameters register (PTPR) allows the user to program
pulsed handshake timings. The port B registers must also be configured for PIP operation. The following
subsections describe the PIP registers.
33.4.1 PIP Configuration Register (PIPC)
The PIP configuration (PIPC) register determines all PIP options.
0 1
Field STR —
Reset
R/W
Addr
This register is effected by HRESET but is not effected by SRESET.
Bits Name
0 STR Start transmit. Applies when T/R = 1 (Tx operation). Setting STR causes the CP to poll the TxBD
table looking for the next TxBD in which the R-bit is set. Prepare TxBDs and buffers before setting
STR. The CP clears STR after one system clock.
1–3 — Reserved, should be cleared.
4 SACK Set acknowledge. When set, SACK asserts the receiver's ACK output regardless of the receiver
state. SACK should be used to implement the IEEE P1284 bidirectional Centronics protocol.
5 CBSY Clear BUSY. When CBSY is set, BUSY is driven low. CBSY is automatically cleared after the PIP
negates BUSY. Set EBSY before using SBSY or CBSY. Note that PIPC[T/R] should be cleared
(receiving) if SBSY or CBSY are used.
6 SBSY Set BUSY. When SBSY is set, BUSY is driven high. SBSY is automatically cleared after the PIP
asserts BUSY. Set EBSY before using SBSY or CBSY. Note that PIPC[T/R] should be cleared
(receiving) if SBSY or CBSY are used.
33-8
Name
— Reserved
RCCR Received control character register. If the newly arrived character matches and is
rejected from the buffer (R = 1), the PIP controller writes the character into the
RCCR and generates a maskable interrupt. If the core does not process the
interrupt and read RCCR before a new control character arrives, the previous
control character is overwritten.
3 4 5 6
SACK CBSY SBSY EBSY
0000_0000_0000_0000
Figure 33-5. PIP Configuration Register (PIPC)
Table 33-6. PIPC Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Figure 33-5
7 8 9 10 11
TMOD MODL
R/W
0xAB2
Table 33-6
Description
shows the register format.
12 13 14 15
MODH HSC T/R
describes PIPC fields.
Freescale Semiconductor