Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 377

Table 13-1 describes each signal; detailed descriptions can be found in subsequent sections.
Signal Pins I/O
A[0:31] 32
Address Bus
RD/WR 1
Read/Write
Freescale Semiconductor
A[0:31]
32
R/W
1
BURST
1
TSIZ[0:1]
2
AT[0:3]
4
PTR
1
RSV
1
STS
1
BDIP
1
TS
1
MPC885
KR/RETRY
1
CR
1
D[0:31]
32
BI
1
TA
1
TEA
1
BR
1
BG
1
BB
1
Figure 13-2. MPC885 Bus Signals
Table 13-1. MPC885 Signal Overview
1
Address and Transfer Attributes
O Driven by the MPC885 when it owns the external bus. Specifies the physical address of
the bus transaction. Can change during a transaction when controlled by the memory
controller.
I Sampled by the MPC885 when an external device initiates a transaction and the
memory controller was configured to handle external master accesses.
O Driven by the MPC885 along with the address when it owns the external bus. Driven high
indicates that a read access is in progress. Driven low indicates that a write access is in
progress.
I Sampled by the MPC885 when an external device initiates a transaction and the
memory controller was configured to handle external master accesses.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Address
and
Transfer
Attributes
Transfer
Start
Reservation
Protocol
Data
Transfer
Cycle
Termination
Arbitration
Description
External Bus Interface
13-3