Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 967

— Serial interface
– Transmission convergence (TC) layer support
– HEC generation/checking
– "Bit aligned" cell delineation eliminates need for byte synchronization signal
– Cell payload scrambling/de-scrambling option (X
– Automatic idle/unassigned cell insertion/stripping
– Cells with incorrect HEC are marked and counted.
• ATM pace control (APC) unit:
— Pace controller with multiple priority levels
– Constant bit rate (CBR) service on a per VC basis
– Real-time and non-real-time variable bit rate (rt-VBR and nrt-VBR) pacing using sustained
cell rate (SCR) and maximum burst size (MBS) parameters
– Unspecified bit rate (UBR) pacing
– Available bit rate (ABR) pacing (pace is managed by upper-layer host software when
establishing a connection)
— Queue handler
– ATM PTP fair queueing mechanism using configurable APC priority levels
– Flexible priority combinations of PTP queues and APC scheduling tables
• Receive address mapping supported by three mechanisms:
— Sequential look-up table (for up to 32 channels)
— Flexible, user-defined address compression mechanism
— Content-addressable memory (CAM)
36.4 MPC885 Application Example
Figure 36-1 shows a possible MPC885 configuration supporting both serial and UTOPIA ATM
transmissions, and Fast Ethernet.
Freescale Semiconductor
MPC885 PowerQUICC Family Reference Manual, Rev. 2
43
+1 polynomial)
ATM Overview
36-5