MPC8xx Core Register Set
Description
General-purpose
registers
Condition register
Table 4-2
lists SPRs defined by the PowerPC architecture implemented on the MPC885.
SPR Number
Decimal SPR [5–9] SPR [0–4]
1
00000
8
00000
9
00000
268
01000
269
01000
1
Extended opcode for mftb, 371 rather than 339.
2
Any write (mtspr) to this address causes an implementation-dependent software emulation exception.
4.1.1.1
PowerPC User-Level Register Bit Assignments
This section describes bit assignments of PowerPC registers implemented by the MPC885. For more
details, see the Programming Environments Manual for 32-Bit Processors.
4.1.1.1.1
Condition Register (
The condition register (CR) is a 32-bit register that reflects the result of certain operations and provides a
mechanism for testing and branching. The bits in the CR are grouped into eight 4-bit fields, CR0–CR7, as
shown in
Figure
4-1.
CR0
CR1
0
3
4
The CR fields can be set in one of the following ways:
•
Specified fields of the CR can be set from a GPR by using the mtcrf instruction.
•
An mcrf instruction can move the contents of XER[0–3] to a CR field.
•
An mcrxr instruction can copy a specified XER field to a specified CR field.
4-2
Table 4-1. User-Level PowerPC Registers
Name
Reference/Section
GPRs The thirty-two 32-bit (GPRs) are used for source
and destination operands.
CR
See
Section 4.1.1.1.1, "Condition Register (CR)."
Table 4-2. MPC885-Specific User-Level SPRs
Name
Reference/Section
00001
XER
See
"XER."
See the Programming
01000
LR
Environments Manual
01001
CTR
See the Programming
Environments Manual
1
01100
TBL read
Section 10.9,
"Timebase"
2
01101
TBU read
CR)
CR2
CR3
7
8
11
12
Figure 4-1. Condition Register (CR)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Access Level Serialize Access
Section 4.1.1.1.3,
Write: Full sync
Read: Sync relative to load/store
operations
No
No
Write (as a store)
CR4
CR5
15
16
19
20
23
User
—
User
Only mtcrf
Serialize Access
CR6
CR7
24
27
28
31
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