Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 196

Exceptions
Number Exception Type
3
7 Privileged instruction
Alignment
System call
Trap
2
8 DTLB miss
2
9 DTLB error
10 Machine check
11 Debug L- breakpoint
1
The trace mechanism is implemented by letting one instruction go as if no trace is enabled and trapping the second
instruction. This, of course, refers to this second instruction.
2
MPC885-specific exception.
3
Exclusive for any one instruction.
When multiple exception conditions exist, only the highest priority exception is taken, as shown in
Table 6-3.
Priority
1 Development port nonmaskable interrupt
2 System reset interrupt
3 Instruction-related exceptions
4 Peripheral breakpoint request or development port maskable interrupt Breakpoint signal from any
5 External interrupt (masked if MSR[EE] = 0)
6 Decrementer interrupt (masked if MSR[EE] = 0)
6.1.2 PowerPC-Defined Exceptions
The following sections describe the exceptions as they are defined by the OEA and describes how they are
implemented on the MPC885.
6.1.2.1 System Reset Interrupt (0x00100)
A system reset interrupt occurs when IRQ0 is asserted. When the exception is taken, processing begins at
offset 0x00100. A hard or soft reset also causes program execution to begin fetching at 0x00100 after the
associated reset actions.
6-4
Table 6-2. Instruction-Related Exception Detection Order
Attempt to execute privileged instruction in user mode
Load/store checking
sc instruction
Trap instruction
Data TLB miss
Data TLB protection/translation error
Load or store access error
2
Match detection
Table 6-3. Exception Priority
Exception Type
Table 6-4 shows register settings.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Cause
Cause
Signal from the development port
IRQ0 assertion
Instruction processing
peripheral
Signal from the interrupt controller
Decrementer request
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