Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 267

Bits Name
28 SPV Subpage validity (subpage 0)
0 Subpage 0 (Address[20–21] = 00) is not valid
1 Subpage 0 (Address[20–21] = 00) is valid
29 0 Subpage 1 (Address[20–21] = 01) is not valid
1 Subpage 1 (Address[20–21] = 01) is valid
30 0 Subpage 2 (Address[20–21] = 10) is not valid
1 Subpage 2 (Address[20–21] = 10) is valid
31 0 Subpage 3 (Address[20–21] = 11) is not valid
1 Subpage 3 (Address[20–21] = 11) is valid
8.8.12.2 IMMU RAM Entry Read Register 0 (MI_RAM0)
The IMMU RAM entry read register 0 (MI_RAM0), shown in
number and page attributes of an entry indexed by MI_CTR[ITLB_INDX]. This register is updated only
when MI_CAM is updated.
0
Field
Reset
R/W
16
Field RPN
Reset
R/W
SPR
Table 8-18 describes MI_RAM0 fields.
Bits Name
0–19 RPN Real (physical) page number
20–22 PS_B Page size. (Values not shown are reserved)
000 4 Kbyte
001 16 Kbyte
011 512 Kbyte
111 8 Mbyte
23 CI Cache-inhibit attribute for the entry.
0 Caching is allowed.
1 Caching is inhibited.
24–27 APG Access protection group. Up to 16 protection groups supported (uses one's complement format)
Freescale Semiconductor
Table 8-17. MI_CAM Field Descriptions (continued)
19 20 22
PS_B
Figure 8-18. IMMU RAM Entry Read Register 0 (MI_RAM0)
Table 8-18. MI_RAM0 Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Function
Figure 8-18, contains the physical page
RPN
—
R
23 24 27
CI APG
—
R
817
Description
Memory Management Unit
15
28 31
SFP
8-25