Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 220

Instruction and Data Caches
Table 7-3 describes the bits of the IC_ADR register.
Bits Name
0–31 ADR Instruction cache command address. When programming the IC_CST[CMD] load-and-lock cache
block and unlock cache block commands, IC_ADR contains the physical address in external
memory of the desired cache block element. When reading the data, tags, and status contained
within the instruction cache, IC_ADR is used to qualify what is to be read according to
See Section 7.3.1.1, "Reading Data and Tags in the Instruction Cache,"
The IC_DAT register, shown in
0
Field
Reset
R/W
SPR
Table 7-4 describes the bits of the IC_DAT register.
Bits Name
0–31 DAT Instruction cache command data. The data received when reading information from the
instruction cache. See
more information.
7.3.1.1 Reading Data and Tags in the Instruction Cache
The MPC885 supports reading the data, tags, and the state and lock bits stored in the instruction cache.
The instruction cache read command, issued by reading the IC_DAT register, uses the IC_ADR register to
qualify what is to be read.
cache read command.
0–16 17
Reserved 0 Tag
1 Data
To read the data or tags stored in the instruction cache, do the following:
1. Write the address of the data or tag to be read to the IC_ADR according to the format in
Note that it is also possible to read this register for debugging purposes.
2. Read the IC_DAT register.
7-8
Table 7-3. Instruction Cache Address Register—IC_ADR
Figure 7-5, has an SPR encoding of 562.
Figure 7-5. Instruction Cache Data Port Register (IC_DAT)
Table 7-4. Instruction Cache Data Port Register—IC_DAT
Section 7.3.1.1, "Reading Data and Tags in the Instruction Cache,"
Table 7-5 describes the fields of the IC_ADR register during an instruction
Table 7-5. IC_ADR Fields for Cache Read Commands
18 19
Reserved 0 = Way 0
1 = Way 1
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
DAT
—
R/W
562
Description
20–27 28–29
Set select Word select
(0–255) (used only for
data array)
Table 7-7.
for more information.
31
for
30–31
Reserved
Table 7-5.
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