Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 585

7. Configure TM_CMD. At this point, determine whether a timer is to be enabled or disabled,
one-shot or restart, and what its timeout period should be. If the timer is being disabled, all
parameters besides the timer number are ignored.
8. Issue
SET TIMER
9. Repeat the steps 7 and 8 for each timer to be enabled or disabled.
As an example, the following sequence demonstrates how RISC timer 0 is initialized to generate an
interrupt approximately every second using a 25-MHz general system clock:
1. Write RCCR[TIMEP] with 0b111111 to generate the slowest timer. This value generates a table
scan tick every 65,536 clocks, which is every 2.6 ms at 25 MHz.
2. Configure TM_BASE to point to a location in the dual-port RAM with 4 bytes available. Assuming
that the beginning of dual-port RAM is available, write 0x0000 to TM_BASE.
3. Write 0x0000 to TM_CNT to see how many ticks have elapsed since the CP internal timer was
enabled (optional).
4. Write 0xFFFF to the RTER to clear any previous events.
5. Write 0x0001 to the RTMR to enable RISC timer 0 to generate an interrupt.
6. Write 0x0002_0000 to the CPM interrupt mask register so the RISC timers generate a system
interrupt. Initialize the CPM interrupt configuration register.
7. Write 0xC000_0EE6 to TM_CMD. This enables RISC timer 0 to timeout after 3,814 (decimal)
ticks. The timer automatically restarts after it times out.
8. Write 0x0851 to the CPCR to issue
9. Set RCCR[TIME] to start RISC timer table scanning.
18.8.7 RISC Timer Interrupt Handling
The following sequence shows what normally occurs within an interrupt handler for the RISC timer table:
1. When an interrupt occurs, read the RTER to see which timers have caused interrupts. The RISC
timer event bits are usually cleared at this time.
2. Issue any additional
the timer is automatically being restarted for repetitive interrupts.
3. Clear CISR[RTT].
4. Execute the rfi instruction.
18.8.8 Using the RISC Timers to Track CP Loading
The RISC timers can be used to track CP loading. The following sequence is a method for using the 16
RISC timers to determine if the CP ever exceeds the 96% utilization level during a scan tick interval.
Removing the timers adds a 4% margin to the CP's utilization level, but an aggressive user can use this
technique to push the CP performance to its limit. Incorporate the following steps to the standard
initialization sequence:
1. Program RCCR[TIMEP] to 0b001111 for a table scan tick of 16 × (1,024) = 16,384.
2. Disable RISC timer table interrupts, if preferred.
Freescale Semiconductor
by writing 0x0851 to the CPCR.
SET TIMER
commands now or later, as preferred. Nothing needs to be done if
SET TIMER
MPC885 PowerQUICC Family Reference Manual, Rev. 2
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Communications Processor
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