Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 232

Instruction and Data Caches
The data path for the instruction cache and its surrounding logic are shown in
Data
32
Bypass
Mux
2->1
To Instruction
Sequencer
The 4-word burst buffer holds the last cache block received from the internal bus (the last miss); the 4-word
block buffer holds the last block retrieved from the instruction cache (the last hit). Note that if one of these
buffers contains the requested instruction, it is also considered a cache hit. To minimize power
consumption, the MPC885 can detect that one of the buffers contains the requested instruction and service
the instruction request from the buffers without activating the instruction cache array.
The MPC885 instruction cache includes the following operational features:
• Instruction fetch latency is reduced by sending the requested instruction address to the instruction
cache and internal bus simultaneously. A cache hit aborts the internal bus transaction before the
MPC885 can initiate an external fetch.
• The instruction cache supports stream hits (allows fetching from the burst buffer or directly from
the internal data bus, before the instruction cache array is filled)
• The instruction cache supports hits under misses (allows servicing hits while a previous miss is
being fetched from the external bus)
7-20
Address [20–27]
Address [28–29]
Stream
Word
32 128
Hit
Select
Mux
Mux
2->1
4->1
Figure 7-9. Instruction Cache Data Path
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Set Instruction Cache
Decoder Array
128
4-Word
128
Cache
Block
128
Buffer
128
32
Figure 7-9.
4-Word
Burst
Buffer
Internal Data Bus
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