Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 149

Branch instructions whose condition is unavailable are issued to the reservation station until they are
predicted. Branch instructions that issue with source data already available do not require prediction (and
are said to be resolved). Instructions fetched under a predicted branch are conditionally fetched. The core
flushes instructions conditionally fetched under a mispredicted branch.
3.4.3.2 Dispatching Instructions
The sequencer can dispatch a sequential instruction on each clock if the appropriate execution unit is
available and a position is free in the completion queue. The execution unit must be able to discern whether
source data is available and to ensure that no other executing instruction targets the same destination
register. The sequencer informs the execution units of the existence of the instruction on the instruction
bus. The execution units decode the instruction, check whether the source and destination operands are
free, and inform the sequencer whether instructions can be dispatched.
3.5 Register Set
Registers implemented in the MPC885 core can be grouped as follows:
• PowerPC registers. The MPC885 implements the user registers defined by the UISA and VEA
portions of the architecture except for those that support floating-point operations. PowerPC
registers implemented on the MPC885 are described in
and Section 4.1.2, "PowerPC Registers—Supervisor Registers."
• Implementation-specific registers. These are all special-purpose registers (SPRs). These are
described in Section 4.1.3, "MPC885-Specific SPRs."
3.6 Execution Units
As shown in Figure 3-1, the MPC885 allows parallel execution of instructions using separate branch
processing unit (BPU), load/store unit (LSU), and integer unit (IU). These execution units are described
in the following sections.
3.6.1 Branch Processing Unit
The branch processing unit differs from the other execution units in that it examines branch instructions
while they are in the IQ. Other instructions are dispatched to the IU and LSU from IQ0. For details about
the performance of various instructions, see
The core supports the UISA-defined static branch prediction. That is, the y bit hints if the branch is likely
to be taken or not taken. No prediction is done for branches to the link register or count register if the target
address is not ready (see
3.6.2 Integer Unit
The core implements the following types of integer instructions:
• Arithmetic instructions
• Compare instructions
Freescale Semiconductor
Table
Table 3-1 for details).
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Chapter 4, "MPC8xx Core Register Set,"
3-1.
The MPC8xx Core
3-9