Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 412

External Bus Interface
13.4.10.1 RETRY
When an external device asserts RETRY during a bus cycle, the MPC885 enters a sequence in which it
terminates the current transaction, relinquishes bus ownership, and retries the cycle using the same
address, address attributes, and data (in the case of a write cycle).
internal arbiter is enabled, the MPC885 negates BB and asserts BG in the clock cycle after RETRY is
detected to allow any external master to gain bus ownership. Normal arbitration resumes in the next clock
cycle. If the external master does not use the bus, the MPC885 initiates a new transfer with the same
address and attributes as before.
CLKOUT
BR
BG (Output)
BB
A[0:31]
R/W
TSIZ[0:1]
BURST
TS
Data
TA
RETRY
13-38
Allow external master
A
Figure 13-29. Retry Transfer Timing–Internal Arbiter
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Figure 13-29
to gain the bus
A
shows that when the
Freescale Semiconductor