Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 896

2
I C Controller
Bits Name
3 I Interrupt
0 No interrupt is generated after this buffer is serviced.
1 I2CER[TXB] or I2CER[TXE] is set when the buffer is serviced. If enabled, an interrupt occurs.
4 L Last
0 This buffer does not contain the last character of the message.
1 This buffer contains the last character of the message. After sending this buffer, the transmitter
generates a stop condition and deactivates. (Retrigger I2COM[STR] to initiate a new
transmission.)
5 S Generate start condition. Provides ability to send back-to-back messages on one I2COM[STR]
trigger.
0 Do not send a start condition before the first byte of the buffer.
1 Send a start condition before the first byte of the buffer. (Used to separate messages.)
Note: If this BD is the first one in a message when I2COM[STR] is triggered, a start condition is sent
regardless of the value of TxBD[S].
6–12 — Reserved and should be cleared.
13 NAK No acknowledge. Indicates that the transmission was aborted because the last byte sent was not
acknowledged. The I
14 UN Underrun. Indicates that the I
sending the associated buffer. The I
15 CL Collision. Indicates that transmission terminated because the transmitter was lost while arbitrating
for the bus. The I
32-14
2
Table 32-10. I C TxBD Status and Control Bits (continued)
2
C controller updates NAK after the buffer is sent.
2
C controller encountered a transmitter underrun condition while
2
C controller updates CL after the buffer is sent.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
2
C controller updates UN after the buffer is sent.
Freescale Semiconductor