Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 825

6. Initialize the RxBD and assume the Rx buffer is at 0x0000_1000 in main memory. Write 0xB000
to RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to
RxBD[Buffer Pointer].
7. Initialize the TxBD and assume the Tx buffer is at 0x0000_2000 in main memory and contains five
8-bit characters. Write 0xB000 to TxBD[Status and Control], 0x0005 to TxBD[Data Length], and
0x0000_2000 to TxBD[Buffer Pointer].
8. Write 0xFF to SMCE to clear any previous events.
9. Write 0x13 to SMCM to enable all possible SMC interrupts.
10. Write 0x0000_0010 to the CIMR so SMC1 can generate a system interrupt. Initialize CICR.
11. Set SMCMR to 0x3830 for 8-bit characters, unreversed data, and normal operation (not loopback).
The transmitter and receiver are not enabled yet.
12. Write 0x3833 to SMCMR to enable the SMC transmitter and receiver. This additional write
ensures that TEN and REN are enabled last.
29.5 SMC in GCI Mode
A single SMC can control both the C/I and monitor channels of a GCI frame. When using the SCIT
configuration of GCI, one SMC can handle SCIT channel 0 and the other can handle SCIT channel 1. The
main features of the SMC in GCI mode are as follows:
• Each SMC channel can support both the C/I and monitor channels of the GCI (IOM-2) in ISDN
applications
• Two SMCs support both sets of C/I and monitor channels in SCIT channels 0 and 1
• Full-duplex operation
• Local loopback and echo capability for testing
To use the SMC GCI channels properly, the TSA must be configured to route the monitor and C/I channels
to the preferred SMC. Chapter 20, "Serial Interface,"
mode is selected by programming SMCMR[SM] to 0b00.
(SMCMRn)," describes other protocol-specific SMCMR bits.
29.5.1 SMC GCI Parameter RAM
The SMC GCI parameter RAM area begins at the same offset from each SMC base. The parameter RAM
differs from that for UART and transparent mode. In GCI mode, parameter RAM contains both the BDs
and their buffers. Compare
no protocol-specific parameter RAM.
1
Offset Name
0x00 M_RxBD
0x02 M_TxBD
Freescale Semiconductor
Table 29-17 with Table 29-2
Table 29-17. SMC GCI Parameter RAM Memory Map
Width
Hword Monitor channel RxBD. See
Hword Monitor channel TxBD. See
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Serial Management Controllers (SMCs)
describes how to program this configuration. GCI
Section 29.2.1, "SMC Mode Registers
to see the differences. In GCI mode the SMC has
Description
Section 29.5.5, "SMC GCI Monitor Channel RxBD."
Section 29.5.6, "SMC GCI Monitor Channel TxBD."
29-31